1. Technical Field
The present invention relates to logic design, and more particularly, to a logic design method to avoid routing congestion.
2. Related Art
In a conventional digital circuit, a logic block can receive signals from multiple inputs from different directions and send signals to multiple outputs at different directions. Typically, the logic block tends to be placed at a central area of the digital circuit surrounded by the inputs and outputs of the logic block. This tends to result in wiring congestion in the central area.
It is always desirable to reduce wiring congestion in logic design. Minimizing wiring congestion improves wirability and reduces the adjacency capacitance impact on timing and noise. As a result, there is a need for a logic design method for reducing wiring congestion in a logic design.